1. Field of the Invention
The present invention relates to mobile communication networks, and especially to interference mitigation for transceivers applying full-duplex radio transmission.
2. Description of the Related Art
Full duplex radio transceivers are capable of transmitting and receiving radio signals simultaneously. A general structure for a radio frequency (RF) transmitter and receiver has been shown in FIG. 1. These RF parts generally locate between a modem and a TX/RX antenna. Also, the RF parts may be formed in a radio frequency integrated circuit (RFIC) which is marked as the dashed box in FIG. 1, besides a duplex filter 16a-b. 
At first considering the receiving signal branch from an antenna 17, the received signal is directed to a duplex filter 16b having an appropriate predetermined bandwidth for the receiving signal. This weak signal is directed to an amplifier 15b. After the amplification the RF signal is down-converted to a baseband signal in a mixer 14b. Thereafter, the down-converted signal is filtered in a low-pass filter 13b. The resulting analogue signal is ready for analogue-digital conversion at relatively high sampling rate, performed by an A/D converter (ADC) 11b. The ADC needs a clock input and this is depicted by a clock 12b. The digitized high-sample signal is thereafter converted to a lower sampling rate in a sampling rate converter (or down-sampler) 10b. This signal can be fed to a demodulator block in the modem.
Correspondingly, the transmission path starting from the modulated digital signal coming out of the modem is at first converted to a higher sampling rate in a sampling rate converter (or up-sampler) 10a. The up-sampled signal is converter from the digital to analogue form in a digital-to-analogue converter (DAC) 11a. For this conversion, the DAC 11a needs some kind of a trigger signal, which can be provided by a digital clock 12a. For mitigating the effect of the harmonics generated by the DAC 11a, the signal is low-pass filtered in 13a and the baseband signal is upconverted in a mixer 14a. The local oscillator signals required by the mixers (14a-b) are left out from the figure. The RF signal is thus amplified in an amplifier 15a before it is fed to the antenna 17 through the duplex filter 16a. 
A problem for such a RF module is that the TX clock 12a signal for the DAC 11a results in harmonic signal components emerging from the TX signal branch and these harmonics propagate along the circuit board as well as through air. These clock harmonics locate at multiples of the fundamental frequency of the clock signal, the amplitude of a harmonic decreasing as an order of the harmonic increases. While the TX signal itself is low-pass-filtered, a significant part of these harmonics may interconnect into the receiving path of the transceiver through other routes on the RFIC board. Though the amplitude of most of the interconnected harmonics is in a very low level, high gain in receiver's RF parts, especially in the amplifier 15b, may lead to a situation where the interfering signal level on the signal detection is sufficiently high in order to degrade the signal reception quality significantly.
The unwanted coupling of the signals from the TX parts to the RX parts may happen through substrate coupling on the circuit board or through magnetic coupling. Interference may emerge also from the power supplies or through any wiring such as ground wiring. For e.g. LTE signal transmission, even the spurious signal amplitudes between −100 . . . −90 dBm can noticeably degrade the signal reception quality.
In prior art, the clock harmonics have been suppressed by designing additional space between functional blocks when a single IC solution is concerned for the whole transceiver. Such spaces act as attenuators for the propagating RF interferences, and as the signal frequency increases, generally the dimensions for such spaces decrease. Regarding the power supplies, decoupling capacitors or shunt circuits can be used for separating the harmful interference sources from the rest of the circuit. Such components require additional silicon area which is an undesired effect because the size of the circuit is an important design criterion.
The jitter effect of the clock signal spreads the power of the clock harmonics over a wider bandwidth but this may cause significant degradation of performance for the functionalities of the ADC and DAC themselves. On the other hand, if the pulse width of the clock signal is altered, the level of individual harmonics may be controlled.
In prior art, methods for suppressing clock harmonics originating from a clock of a microprocessor have been presented. E.g. in US 2006/0057970, it concerns a method and a system for reducing effects of clock harmonic frequencies. The clock frequency of the microprocessor can be selected and also the passband of the receiver side can be selected according e.g. to a desired operational mode of the transceiver in a way that the spurious signals originating from the clock harmonics do not interfere with the transceiver passband signal.
In prior art, there has not been presented an efficient method for mitigating the effect of harmonics originating from the clock frequency defining the sample rate and operational frequency of the TX digital-to-analogue converter (DAC).